Electronic devices using carbon nanotubes having vertical structure and the manufacturing method thereof

ABSTRACT

Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same. The method of manufacturing an electronic device having a vertical CNT includes the steps of: (a) preparing a substrate on which a silicon source is formed; (b) forming a first insulating layer on the substrate, and etching the first insulating layer such that a top surface of the silicon source is exposed; (c) forming a second insulating layer on the silicon source, and forming a gate by patterning the second insulating layer; (d) forming a third insulating layer on the gate, and forming a through hole in which a carbon nanotube channel is to be formed by etching the third insulating layer and the second insulating layer; (e) forming a fourth insulating layer surrounding the gate on the through hole and the third insulating layer, and forming a spacer by etching the fourth insulating layer; (f) forming a metal catalyst on the silicon source; (g) vertically growing the carbon nanotube channel on the silicon source using the metal catalyst; (h) forming a fifth insulating layer on the through hole in which the carbon nanotube is formed and the third insulating layer; and (i) patterning the fifth insulating layer such that the carbon nanotube channel is exposed, and forming a silicon drain. An arrangement problem of horizontal CNTs can be solved by applying vertical CNTs and a selective silicon growth technique.

TECHNICAL FIELD

The present invention relates to a method of manufacturing an electronicdevice using carbon nanotubes (CNTs), and more particularly, to a methodof manufacturing an electronic device having a vertical CNT channelgrown by a selective vertical growth technique.

The present invention has been produced from the work supported by theIT R&D program of MIC (Ministry of Information and Communication)/IITA(Institute for Information Technology Advancement) [2005-S-073-02,Development of semiconductor circuit design based on the nano-scaleddevice] in Korea.

BACKGROUND ART

Recently developed electronic devices based on silicon have decreased insize to several tens of nm. As the sizes of electronic devices decrease,it becomes more difficult to flow sufficient current through aconventional silicon channel, and so the channel has to be highly dopedto increase current density, which is also difficult. Accordingly, tomanufacture electronic devices which do not need channel doping and canbe operated at a low current, horizontal CNTs of less than several tensof nm in diameter have recently been applied to a channel of anultra-fine electronic device. Generally, CNTs exhibit metallic orsemiconductor characteristics depending on contact condition, and thusan electronic device having a horizontal CNT channel employs CNTs havingsemiconductor characteristics.

An electronic device using conventional CNTs will now be described withreference to FIG. 1.

FIG. 1 illustrates a conventional electronic device using horizontalCNTs.

Referring to FIG. 1, a conventional CNT electronic device 100 includes asilicon substrate 101, an oxide 102 formed thereon, a source 103 and adrain 104 formed over the oxide 102, a CNT channel 105 formed betweenthe source 103 and the drain 104 to horizontally connect the source 103with the drain 104, and a gate 106 formed on the CNT channel 105.

To operate the electronic device 100 having such a structure, first,voltage has to be applied to the gate 106. If the voltage is applied tothe gate 106, a current path of the CNT channel 105 is turned on,thereby operating the electronic device 100, otherwise the current pathof the CNT channel 105 is turned off.

However, in manufacturing the conventional CNT electronic device, it isdifficult to apply standardized CNTs which have uniform length andelectrical characteristics, and it is also difficult to preciselyarrange the CNTs between the silicon source and the silicon drain. Whilea technique using a physical adsorption characteristic has recently beenused, it has also shown difficulty in uniformly arranging CNTs. Thus, itis difficult to mass-produce such devices, and defects and contaminationof the devices may result.

DISCLOSURE OF INVENTION Technical Problem

The present invention is directed to a method of manufacturing anelectronic device which can arrange carbon nanotubes (CNTs) in accuratepositions and improve a contact characteristic of the CNT by including avertical CNT channel formed by a selective vertical growth technique ofthe CNTs.

Technical Solution

One aspect of the present invention provides a method of manufacturingan electronic device using a vertical carbon nanotube (CNT), includingthe steps of: (a) preparing a substrate on which a silicon source isformed; (b) forming a first insulating layer on the substrate, andetching the first insulating layer such that a top surface of thesilicon source is exposed; (c) forming a second insulating layer on thesilicon source, and forming a gate by patterning the second insulatinglayer; (d) forming a third insulating layer on the gate, and forming athrough hole in which a carbon nanotube channel is to be formed byetching the third insulating layer and the second insulating layer; (e)forming a fourth insulating layer surrounding the gate on the throughhole and the third insulating layer, and forming a spacer by etching thefourth insulating layer; (f) forming a metal catalyst on the siliconsource; (g) vertically growing the carbon nanotube channel on thesilicon source using the metal catalyst; (h) forming a fifth insulatinglayer on the through hole in which the carbon nanotube is formed and thethird insulating layer; and (i) patterning the fifth insulating layersuch that the carbon nanotube channel is exposed, and forming a silicondrain.

The substrate may be a silicon on insulator (SOI) substrate or apolycrystalline silicon substrate.

Step (c) may include the steps of: coating the second insulating layerwith photoresist (PR), and patterning the PR by exposure; etching thesecond insulating layer using the patterned photoresist to form a gatehole, and removing the PR; forming a gate material over the secondinsulating layer and in the gate hole; and removing the gate materialformed over the second insulating layer, except for the gate materialformed in the gate hole, by etching.

Step (d) may include the steps of: coating the third insulating layerwith PR, and patterning the PR by exposure; etching the second and thirdinsulating layers to form the through hole; and removing the PR on thethird insulating layer.

Step (f) may include the steps of: forming a metal catalyst particle inthe air and dropping it onto the silicon source and the third insulatinglayer; annealing the metal catalyst particle in a vacuum; and removingthe metal particles on the third insulating layer.

Step (i) may include the steps of: coating the fifth insulating layerwith PR, and patterning the fifth insulating layer by exposure; etchingthe fifth insulating layer until an end portion of the CNT is exposed;removing the PR on the fifth insulating layer; and forming a silicondrain on the fifth insulating layer.

Step (c) may include the steps of: coating the second insulating layerwith PR, and patterning the PR by exposure; etching the secondinsulating layer using the patterned PR to form gate holes at both sidesof the silicon source, respectively, and removing the PR; and forming agate material over the second insulating layer and in the gate hole.

Step (i) may include the steps of: coating the fifth insulating layerwith PR, and patterning the fifth insulating layer by exposure; etchingthe fifth insulating layer until an end portion of the CNT is exposed;removing the PR on the fifth insulating layer; cleaning an etchedsurface of the fifth insulating layer; and forming a drain byselectively growing silicon on the etched surface.

The metal catalyst in step (g) may be one of Fe, Ni, Pt, Pd, Cu, Au andAl.

The gate material in step (c) may be one of metal, silicide, and dopedsilicon.

Another aspect of the present invention provides an electronic deviceusing a vertical CNT, including: a silicon source formed on a substrate;a first insulating layer exposing a top surface of the silicon sourceand formed on the substrate; a second insulating layer formed on thefirst insulating layer and having a through hole exposing the siliconsource; at least one carbon nanotube grown perpendicular to a topsurface of the silicon source exposed through the through hole; at leastone gate formed parallel to the growth direction of the carbon nanotubeto be in contact with the through hole; and a silicon drain connected toan end portion of the carbon nanotube exposed through the through hole.

The gate may be formed of one of metal, silicide, and doped silicon.

The substrate may be an SOI substrate or a polycrystalline siliconsubstrate. The length of the CNT may be 50 to 250 nm.

The silicon drain may be formed by a selective silicon growth technique.The through hole in which the CNT is formed may be filled with aninsulating layer.

Advantageous Effects

As described above, the present invention uses a carbon nanotube (CNT)having a vertical structure, and applies a selective silicon growthtechnique, thereby solving an arrangement problem of CNTs having ahorizontal structure.

Also, since the CNT is formed in a vertical structure, it can realize ahighly integrated device more than twice that formed in a horizontalstructure, and a dual gate structure can be simply formed by disposinggates at both sides of a CNT channel.

Using a selective silicon growth technique, the CNTs can be connected toeach other, thereby simplifying processes, improving a contactcharacteristic, and increasing reliability of the process ofmanufacturing an electronic device using CNTs to increase a rippleeffect on related technology in the future.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional electronic device using horizontalcarbon nanotubes (CNTs).

FIGS. 2A to 5D are cross-sectional views illustrating a process ofmanufacturing an electronic device according to an exemplary embodimentof the present invention.

FIG. 6A to 6C are cross-sectional views illustrating a process ofmanufacturing a dual gate electronic device according to anotherexemplary embodiment of the present invention.

FIG. 7 illustrates a silicon drain formed by selective silicon growth.

DESCRIPTION OF MAJOR SYMBOLS IN THE ABOVE FIGURES

-   -   1: Substrate    -   1 a: Silicon layer    -   1 b: Lower insulating layer    -   2, 6, 9, 15 and 17: PR pattern    -   3: Silicon source    -   4: First insulating layer    -   5: Second insulating layer    -   5 a and 8 a: Contact hole    -   6 a, 9 a and 17 a: Opening    -   7: Gate    -   7 a: Gate material    -   8: Third insulating layer    -   10: Fourth insulating layer    -   11: Spacer    -   12: Metal catalyst particle    -   13: Carbon nanotube    -   14: Fifth insulating layer    -   16: Silicon drain    -   18: Silicon drain formed by selective silicon growth

MODE FOR THE INVENTION

Hereinafter, a method of manufacturing an electronic device using avertical carbon nanotube (CNT) channel according to the presentinvention will be described with reference to the accompanying FIGS. 2Ato 5D.

FIGS. 2A to 5D are cross-sectional views illustrating a process ofmanufacturing a vertical CNT electronic device according to an exemplaryembodiment of the present invention.

Referring to FIG. 2A, to manufacture an electronic device including avertical CNT channel, a substrate 1 is first prepared.

The substrate 1 is usually a silicon on insulator (SOI) substrate inwhich a silicon layer 1 a is formed on a lower insulating layer 1 b.However, the substrate 1 can be a polycrystalline silicon substrateformed by thermally oxidizing a silicon surface. The lower insulatinglayer 1 b may be formed of oxide or nitride.

Then, a photoresist (PR) 2 a is coated on the substrate 1 and patternedby exposure and patterning to form a PR pattern 2 for forming a siliconsource.

Referring to FIG. 2B, the silicon layer 1 a is etched using thepatterned PR 2, thereby forming a silicon source 3. To etch the siliconlayer 1 a, a dry etching process is used, and an ashing process isperformed to remove the PR pattern 2. In this embodiment, O₂ ashing isused. The patterned silicon source 3 has a height and width of 10 to 100nm, respectively.

Then, referring to FIG. 2C, a first insulating layer 4 is formed on thesubstrate 1 having the silicon source 3. The first insulating layer 4may be formed of oxide or nitride to cover the entire silicon source 3.

Referring to FIG. 2D, the first insulating layer 4 formed to cover thesilicon source 3 is etched, thereby exposing a top surface of thesilicon source 3. Here, the first insulating layer 4 is removed byblanket etching or chemical mechanical polishing (CMP).

Referring to FIGS. 3A and 3B, a second insulating layer 5 may be formedto a thickness of 20 to 200 nm on the first insulating layer 4 havingthe silicon source 3 whose top surface is exposed. The second insulatinglayer 5 is formed using an oxide layer having good vertical etchabilityby high density plasma (HDP) deposition, or by flowing a coatedboro-phospho silicate glass (BPSG) layer. A photoresist (PR) 6 is coatedon the second insulating layer 5, and then patterned to form an opening6 a for forming a gate electrode. Here, the opening 6 a for forming agate electrode may have a width of 10 to 100 nm.

A contact hole 5 a is formed in the second insulating layer 5 using thePR pattern 6 having the opening 6 a as an etch mask by dry etching.Here, if the first insulating layer 4 is different from the secondinsulating layer 5 (for example, the first insulating layer is a nitridelayer, and the second insulating layer is an oxide layer), the firstinsulating layer 4 is not affected during the etching of the secondinsulating layer 5. However, if both the insulating layers 4 and 5 areformed of the same material, the first insulating layer 4 may getdamaged during the etching of the second insulating layer 5, so thesecond insulating layer 5 is etched by dry etching having a high etchselectivity in order not to damage the first insulating layer 4.

After forming the contact hole 5 a, the PR pattern 6 formed on thesecond insulating layer 5 is removed. Then, a gate material 7 a isformed on the contact hole 5 a and the second insulating layer 5. Thegate material 7 a may be one of metal (tungsten (W), a W alloy, etc.),silicide (W-silicide, nickel (Ni)-silicide, etc.) and doped silicon.

In the next step, referring to FIG. 3C, a gate 7 is formed by removingthe gate material 7 a formed on the second insulating layer 5, exceptfor the gate material 7 a in the contact hole 5 a, by blanket-etching orCMP. After removal of the gate material 7 a, a third insulating layer 8is deposited on the second insulating layer 5. The third insulatinglayer 8 may be formed of oxide or nitride.

Referring to FIGS. 3D and 4A, a PR pattern 9 having an opening 9 a isformed on the third insulating layer 8. The opening 9 a is formed to bespaced apart from the gate 7, and the third insulating layer 8 and thesecond insulating layer 5 are dry-etched using the PR pattern 9 havingthe opening 9 a, thereby forming a contact hole 8 a. Here, only thethird insulating layer 8 and the second insulating layer 5 are etchednot to damage the silicon source 3. Then, a fourth insulating layer 10having good step coverage is formed on the exposed silicon source 3 andthe third insulating layer 8. The fourth insulating layer 10 may beformed to a thickness of 5 to 50 nm using a nitride layer or an oxidelayer.

Referring to FIG. 4B, the fourth insulating layer 10 is etched to form aspacer 11. The spacer 11 may be formed to a thickness of 2 to 20 nm notto expose the gate 7. After that, a cleaning process is performed toremove etching damage to the silicon source due to etching, because theetching damage may affect contact characteristics between the CNT andsilicon.

FIG. 4C is a cross-sectional view illustrating a process of forming ametal catalyst particle. The metal catalyst particle 12 may be formed ofmetal such as iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd),copper (Cu), gold (Au) or aluminum (Al), and may have a diameter of 2 to20 nm. The metal catalyst particle is formed in the air and then droppedonto the substrate. After that, the particle is annealed in a vacuum ata temperature of 500° C. or less, and thus the metal catalyst particle12 and the silicon source 3 are strongly bonded to each other. Here, ifthe annealing is performed at too high a temperature or for too long atime, the metal catalyst particle 12 can penetrate into the silicon.After annealing the metal catalyst particle 12 and the silicon source 3,an ultra-sonic cleaning or laser shock cleaning process is performed toremove the metal catalyst particles 12 from the third insulating layer8.

Referring to FIG. 4D, a CNT 13 is vertically grown after leaving themetal catalyst particle 12 only on the silicon source 3. The CNT 13 maybe 50 to 250 nm long, and may be grown to be a single wall CNT (SWCNT).The CNT growth methods (which include chemical vapor deposition (CVD),vapor phase growth, plasma enhanced chemical vapor deposition (PECVD),arc-discharging and laser deposition) may have a slow growth rate andprecisely control the CNT's length.

Referring to FIG. 5A, after growing the CNT 13, the spacer 11 is removedby etching, and a fifth insulating layer 14 having good step coverage isformed. The fifth insulating layer 14 may be formed of oxide or nitride.Then, to form a silicon drain connected with the CNT 13, a photoresist(PR) 15 is coated on the fifth insulating layer 14 and then patterned.

Referring to FIG. 5B, the fifth insulating layer 14 is etched to exposean end portion of the CNT 13 vertically formed, and the PR pattern 15 isremoved.

Referring to FIG. 5C, a silicon drain 16 is deposited on the fifthinsulating layer 14 to be connected with the CNT 13.

Referring to FIG. 5D, the silicon on the fifth insulating layer 14 isremoved by blanket-etching or CMP.

The method of manufacturing a vertical CNT electronic device has beendescribed with reference to FIGS. 2A to 5D, according to an exemplaryembodiment of the present invention. A method according to anotherexemplary embodiment of the present invention will now be described withreference to FIGS. 6A to 6C, and FIG. 7.

FIGS. 6A to 6C are cross-sectional views illustrating a process ofmanufacturing a vertical CNT electronic device having a dual gate.

Referring to FIG. 6A, instead of a PR process for forming one gate suchas that in

FIG. 3A, a PR patterning process 17 is performed to form an opening 17a, thereby forming two gates at both sides of the silicon source.

Next, referring to FIG. 6B, a contact hole 5 a is formed in a secondinsulating layer 5 using the PR pattern 17 by dry etching, asillustrated in FIG. 3B, and then is filled with a gate material 7 a.

Other processes are the same as those illustrated in FIGS. 2A to 2D and3C to 5D, and thus may be analogized therefrom.

FIG. 6C illustrates a completed vertical CNT electronic device having adual gate.

FIG. 7 illustrates a drain formed by a selective silicon growthtechnique.

After the process is completed with reference to FIGS. 2A to 5A, a fifthinsulating layer 14 is etched, cleaned and then grown by the selectivesilicon growth technique as illustrated in FIG. 5B. In the selectivesilicon growth technique, the process of blanket-etching a silicon thinfilm after forming the silicon thin film may be omitted. Since the CNTis a conductor, a drain 18 can be filled with silicon by the selectivesilicon growth.

While the invention has been shown and described with reference tocertain exemplary embodiments thereof, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims.

1. A method of manufacturing an electronic device using a verticalcarbon nanotube, comprising the steps of: (a) preparing a substrate onwhich a silicon source is formed; (b) forming a first insulating layeron the substrate, and etching the first insulating layer such that a topsurface of the silicon source is exposed; (c) forming a secondinsulating layer on the silicon source, and forming a gate by patterningthe second insulating layer; (d) forming a third insulating layer on thegate, and forming a through hole in which a carbon nanotube channel isto be formed by etching the third insulating layer and the secondinsulating layer; (e) forming a fourth insulating layer surrounding thegate on the through hole and the third insulating layer, and forming aspacer by etching the fourth insulating layer; (f) forming a metalcatalyst on the silicon source; (g) vertically growing the carbonnanotube channel on the silicon source using the metal catalyst; (h)forming a fifth insulating layer on the through hole in which the carbonnanotube channel is formed and the third insulating layer; and (i)patterning the fifth insulating layer such that the carbon nanotubechannel is exposed, and forming a silicon drain at the carbon nanotubechannel exposed region, wherein the carbon nanotube channel is connectedbetween the silicon source and the silicon drain.
 2. The methodaccording to claim 1, wherein the substrate is a silicon on insulator(SOI) substrate or a polycrystalline silicon substrate.
 3. The methodaccording to claim 1, wherein step (c) comprises the steps of: coatingthe second insulating layer with photoresist and patterning thephotoresist by exposure; etching the second insulating layer using thepatterned photoresist to form a gate hole, and removing the photoresist;depositing a gate material over the second insulating layer and in thegate hole; and removing the gate material deposited over the secondinsulating layer, except for the gate material deposited in the gatehole, by etching.
 4. The method according to claim 1, wherein step (d)comprises the steps of: coating the third insulating layer withphotoresist, and patterning the photoresist by exposure; etching thesecond and third insulating layers to form the through hole; andremoving the photoresist on the third insulating layer.
 5. The methodaccording to claim 1, wherein step (f) comprises the steps of: forming ametal catalyst particle in the air, and dropping the metal catalystparticle onto the silicon source and the third insulating layer;annealing the metal catalyst particle in a vacuum; and removing themetal catalyst particles on the third insulating layer.
 6. The methodaccording to claim 1, wherein step (i) comprises the steps of: coatingthe fifth insulating layer with photoresist, and patterning the fifthinsulating layer by exposure; etching the fifth insulating layer untilan end portion of the carbon nanotube channel is exposed; removing thephotoresist on the fifth insulating layer; and forming a silicon drainon the fifth insulating layer.
 7. The method according to claim 1,wherein step (c) comprises the steps of: coating the second insulatinglayer with photoresist, and patterning the photoresist by exposure;etching the second insulating layer using the patterned photoresist toform gate holes at both sides of the silicon source, respectively, andremoving the photoresist; and depositing a gate material over the secondinsulating layer and in the gate hole.
 8. The method according to claim1, wherein step (i) comprises the steps of: coating the fifth insulatinglayer with photoresist, and patterning the fifth insulating layer byexposure; etching the fifth insulating layer until an end portion of thecarbon nanotube channel is exposed; removing the photoresist on thefifth insulating layer; cleaning an etched surface of the fifthinsulating layer; and forming a drain by selectively growing silicon onthe etched surface.
 9. The method according to claim 1, wherein themetal catalyst in step (g) is one of Fe, Ni, Pt, Pd, Cu, Au and Al. 10.The method according to claim 1, wherein the gate material in step (c)is one of metal, silicide, and doped silicon.
 11. An electronic devicehaving a vertical carbon nanotube, comprising: a silicon source formedon a substrate; a first insulating layer exposing a top surface of thesilicon source and formed on the substrate; a second insulating layerformed on the first insulating layer and having a through hole exposingthe silicon source; at least one carbon nanotube perpendicularly grownfrom a top surface of the silicon source exposed by the through hole; atleast one gate formed parallel to the growth direction of the carbonnanotube to be in contact with the through hole; a third insulatinglayer filled in the through hole in which the carbon nanotube is formed;and a silicon drain formed on the through hole in which the carbonnanotube and the third insulating layer are formed and connected to anend portion of the carbon nanotube, wherein the carbon nanotube isconnected between the silicon source and the silicon drain.
 12. Thedevice according to claim 11, wherein the gate is formed of one ofmetal, silicide, and doped silicon.
 13. The device according to claim11, wherein the substrate is an SOI substrate or a polycrystallinesilicon substrate.
 14. The device according to claim 11, wherein thelength of the carbon nanotube ranges from 50 to 250 nm.
 15. The deviceaccording to claim 11, wherein the silicon drain is formed byselectively growing silicon.
 16. The method according to claim 1,wherein one end of the carbon nanotube channel is in direct contact withthe silicon source and the other end of the carbon nanotube channel isin direct contact with the silicon drain.
 17. The device according toclaim 11, wherein one end of the carbon nanotube is in direct contactwith the silicon source and the other end of the carbon nanotube is indirect contact with the silicon drain.
 18. The device according to claim11, wherein the carbon nanotube extends in a direction perpendicular toa direction in which the substrate extends.
 19. The device according toclaim 11, wherein the carbon nanotube extends in a directionperpendicular to a direction in which the substrate extends, with oneend of the carbon nanotube being in direct contact with the siliconsource and the other end of the carbon nanotube being in direct contactwith the silicon drain.